This tutorial goes over all the information you need to create your own custom elements.
Pinout
VIDEO
The Alchitry V2 boards have
three DF40
connectors on a side.
The 50-pin connector is the Control header.
It has pins for power and miscellaneous control and status pins.
The two 80-pin connectors have up to 52 IO pins on each with the remaining pins being used as grounds.
The connector closest to the Control header is Bank A and the other is Bank B .
The 50-pin connector is DF40HC(4.0)-50DS-0.4V(51) when used on the top and the mating DF40C-50DP-0.4V(51) when on
the bottom.
The 80-pin connectors are DF40HC(4.0)-80DS-0.4V(51) when used on the top and the mating DF40C-80DP-0.4V(51) when on
the bottom.
Pin 1 of each connector is at the bottom left for each in the image above.
The pinout of each board follows a general template, but they all vary a little from each other.
See below for the full pinouts.
Cu
Cu Schematic
Pinout Table
Show Trace Delays
Bank A
Delay [ps] GND 1
2
GND Delay [ps]
98
IO 3
4
IO 161
103
IO 5
6
IO 152
GND 7
8
GND
94
IO 9
10
IO 159
91
IO 11
12
IO 161
GND 13
14
GND
106
IO 15
16
IO 154
93
IO 17
18
IO 149
GND 19
20
GND
99
IO 21
22
IO 160
93
IO 23
24
IO 147
GND 25
26
GND
101
IO 27
28
IO 159
95
IO 29
30
IO 156
GND 31
32
GND
103
IO 33
34
IO 136
97
IO 35
36
IO 136
GND 37
38
GND
104
IO 39
40
IO 139
98
IO - GBIN 41
42
IO - GBIN 185
GND 43
44
GND
106
IO 45
46
IO 133
100
IO - GBIN 47
48
IO - GBIN 182
GND 49
50
GND
98
IO 51
52
IO 135
106
IO 53
54
IO 139
GND 55
56
GND
100
IO 57
58
IO 147
108
IO 59
60
IO 150
GND 61
62
GND
102
IO 63
64
IO 156
150
IO 65
66
IO 160
GND 67
68
GND
150
IO 69
70
IO 145
148
IO 71
72
IO 141
GND 73
74
GND
158
IO 75
76
IO 153
156
IO 77
78
IO 150
GND 79
80
GND
Bank B
Delay [ps] GND 1
2
GND Delay [ps]
126
IO 3
4
IO 86
134
IO 5
6
IO 96
GND 7
8
GND
123
IO 9
10
IO 87
132
IO 11
12
IO 94
GND 13
14
GND
121
IO 15
16
IO 89
118
IO 17
18
IO 97
GND 19
20
GND
127
IO 21
22
IO 91
135
IO 23
24
IO 95
GND 25
26
GND
134
IO 27
28
IO 89
140
IO 29
30
IO 97
GND 31
32
GND
113
IO - SDA 33
34
IO - CBSEL0 117
126
IO - SCL 35
36
IO - CBSEL1 97
GND 37
38
GND
138
IO 39
40
-
138
IO - GBIN 41
42
IO - GBIN 123
GND 43
44
GND
- 45
46
-
- 47
48
-
GND 49
50
GND
- 51
52
-
- 53
54
-
GND 55
56
GND
- 57
58
-
- 59
60
-
GND 61
62
GND
- 63
64
-
- 65
66
-
GND 67
68
GND
- 69
70
-
- 71
72
-
GND 73
74
GND
- 75
76
-
- 77
78
-
GND 79
80
GND
Control
+3.3V 1
2
VDD
+3.3V 3
4
VDD
+3.3V 5
6
VDD
+3.3V 7
8
VDD
+3.3V 9
10
VDD
+3.3V 11
12
VDD
+3.3V 13
14
VDD
+3.3V 15
16
VDD
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
LED 0 29
30
LED 4
LED 1 31
32
LED 5
LED 2 33
34
LED 6
LED 3 35
36
LED 7
RESET 37
38
-
DONE 39
40
-
C_RESET 41
42
-
ICE SS 43
44
-
ICE SCK 45
46
-
ICE MISO 47
48
-
ICE MOSI 49
50
-
Legend
IO Standard IO. SDA and SCL also connect to the QWIIC connector
GBIN Clock capable input
CONFIG Configuration signal. CBSELn can be used to select one of multiple boot images
+3.3V 3.3V output
VDD 5V-12V board power. When plugged into USB, this can supply 5V. The USB port is protected against
higher voltages
GND Ground
- No connection
Au
Au Schematic
Pinout Table
Bank A
Delay [ps] GND 1
2
GND Delay [ps]
418
IO N 3
4
IO N 437
418
IO P 5
6
IO P 437
GND 7
8
GND
254
IO N 9
10
IO N 308
259
IO P 11
12
IO P 306
GND 13
14
GND
217
IO N 15
16
IO N 270
216
IO P 17
18
IO P 259
GND 19
20
GND
310
IO N 21
22
IO N 277
309
IO P 23
24
IO P 275
GND 25
26
GND
243
IO N 27
28
IO N 252
249
IO P 29
30
IO P 262
GND 31
32
GND
284
IO N 33
34
IO N 265
283
IO P 35
36
IO P 268
GND 37
38
GND
274
IO N - MRCC 39
40
IO N - SRCC 286
269
IO P - MRCC 41
42
IO P - SRCC 282
GND 43
44
GND
342
IO N - MRCC 45
46
IO N - SRCC 372
341
IO P - MRCC 47
48
IO P - SRCC 371
GND 49
50
GND
232
IO N 51
52
IO N 272
234
IO P 53
54
IO P 275
GND 55
56
GND
229
IO N A 57
58
IO N A 287
231
IO P A 59
60
IO P A 286
GND 61
62
GND
316
IO N A 63
64
IO N A 294
306
IO P A 65
66
IO P A 286
GND 67
68
GND
314
IO N A 69
70
IO N A 289
316
IO P A 71
72
IO P A 286
GND 73
74
GND
281
IO N A 75
76
IO N A 280
277
IO P A 77
78
IO P A 282
GND 79
80
GND
Bank B
Delay [ps] GND 1
2
GND Delay [ps]
206
IO N 3
4
IO N 174
208
IO P 5
6
IO P 176
GND 7
8
GND
235
IO N 9
10
IO N 171
231
IO P 11
12
IO P 172
GND 13
14
GND
249
IO N 15
16
IO N 157
250
IO P 17
18
IO P 163
GND 19
20
GND
252
IO N 21
22
IO N 163
257
IO P 23
24
IO P 161
GND 25
26
GND
251
IO N 27
28
IO N 157
257
IO P 29
30
IO P 155
GND 31
32
GND
297
IO - SDA 33
34
IO N 176
355
IO - SCL 35
36
IO P 186
GND 37
38
GND
278
IO N - SRCC 39
40
IO N - SRCC 226
283
IO P - SRCC 41
42
IO P - SRCC 224
GND 43
44
GND
267
IO N - MRCC 45
46
IO - 1.35V 288
269
IO P - MRCC 47
48
IO - 1.35V 265
GND 49
50
GND
324
IO N MV 51
52
IO N MV 288
330
IO P MV 53
54
IO P MV 290
GND 55
56
GND
297
IO N MV 57
58
IO N MV 295
298
IO P MV 59
60
IO P MV 292
GND 61
62
GND
307
IO N MV 63
64
IO N MV 295
302
IO P MV 65
66
IO P MV 293
GND 67
68
GND
358
IO N MV 69
70
IO N MV 291
353
IO P MV 71
72
IO P MV 290
GND 73
74
GND
312
IO N MV 75
76
IO N MV 294
318
IO P MV 77
78
IO P MV 295
GND 79
80
GND
Control
+3.3V 1
2
VDD
+3.3V 3
4
VDD
+3.3V 5
6
VDD
+3.3V 7
8
VDD
+3.3V 9
10
VDD
+3.3V 11
12
VDD
+3.3V 13
14
VDD
+3.3V 15
16
VDD
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
LED 0 29
30
LED 4
LED 1 31
32
LED 5
LED 2 33
34
LED 6
LED 3 35
36
LED 7
RESET 37
38
VBSEL A
DONE 39
40
VBSEL B
PROGRAM 41
42
A1.8V
TMS 43
44
AV P
TCK 45
46
AV N
TDI 47
48
AREF
TDO 49
50
AGND
VBSEL Values
VBSEL A
VBSEL B
MV VCCO
floating
floating
3.3
low
low
3.3
low
high
3.3
high
low
1.8
high
high
2.5
VBSEL B
VBSEL A
2.5
low = 0-0.9 volts
Legend
IO Standard IO. SDA and SCL also connect to the QWIIC connector. The 1.35V
pins are not 3.3V tolerant
IO N/P Differential capable IO
MRCC/SRCC Clock capable input. Single ended clocks must go to the P pin of the pair
Multi-voltage Multi-voltage pin. The VCCO for these pins is controllable via VBSEL A and VBSEL
B
Analog Analog signal. IO N/P A and AV P/N are 1V inputs
CONFIG Configuration signal
+3.3V 3.3V output
VDD 5V-12V board power. When plugged into USB, this can supply 5V. The USB port is protected against
higher voltages
GND Ground
† Delays include trace and package delays
Pt
Pt Schematic
Top Pinout Table
Bank A
Delay [ps] GND 1
2
GND Delay [ps]
452
IO N 3
4
IO N 469
459
IO P 5
6
IO P 472
GND 7
8
GND
257
IO N 9
10
IO N 378
265
IO P 11
12
IO P 387
GND 13
14
GND
319
IO N 15
16
IO N 340
323
IO P 17
18
IO P 345
GND 19
20
GND
266
IO N 21
22
IO N 318
270
IO P 23
24
IO P 318
GND 25
26
GND
311
IO N 27
28
IO N 334
311
IO P 29
30
IO P 336
GND 31
32
GND
412
IO N 33
34
IO N 424
407
IO P 35
36
IO P 412
GND 37
38
GND
294
IO N - MRCC 39
40
IO N - SRCC 368
295
IO P - MRCC 41
42
IO P - SRCC 371
GND 43
44
GND
310
IO N - MRCC 45
46
IO N - SRCC 432
312
IO P - MRCC 47
48
IO P - SRCC 441
GND 49
50
GND
445
IO N 51
52
IO N 498
457
IO P 53
54
IO P 487
GND 55
56
GND
334
IO N A 57
58
IO N A 392
337
IO P A 59
60
IO P A 394
GND 61
62
GND
377
IO N A 63
64
IO N A 396
377
IO P A 65
66
IO P A 399
GND 67
68
GND
354
IO N A 69
70
IO N A 420
355
IO P A 71
72
IO P A 421
GND 73
74
GND
434
IO N A 75
76
IO N A 438
437
IO P A 77
78
IO P A 442
GND 79
80
GND
Bank B
Delay [ps] GND 1
2
GND Delay [ps]
200
IO N 3
4
IO N 203
213
IO P 5
6
IO P 196
GND 7
8
GND
272
IO N 9
10
IO N 183
272
IO P 11
12
IO P 177
GND 13
14
GND
217
IO N 15
16
IO N 164
217
IO P 17
18
IO P 165
GND 19
20
GND
234
IO N 21
22
IO N - SRCC 231
240
IO P 23
24
IO P - SRCC 243
GND 25
26
GND
225
IO N - MRCC 27
28
IO N - SRCC 229
227
IO P - MRCC 29
30
IO P - SRCC 228
GND 31
32
GND
304
IO N MV 33
34
IO N MV 233
303
IO P MV 35
36
IO P MV 239
GND 37
38
GND
468
IO N MV - MRCC 39
40
IO N MV - SRCC 260
464
IO P MV - MRCC 41
42
IO P MV - SRCC 262
GND 43
44
GND
318
IO N MV - MRCC 45
46
IO N MV - SRCC 244
322
IO P MV - MRCC 47
48
IO P MV - SRCC 242
GND 49
50
GND
351
IO N MV 51
52
IO N MV 281
351
IO P MV 53
54
IO P MV 294
GND 55
56
GND
307
IO N MV 57
58
IO N MV 316
314
IO P MV 59
60
IO P MV 321
GND 61
62
GND
330
IO N MV 63
64
IO N MV 285
327
IO P MV 65
66
IO P MV 292
GND 67
68
GND
323
IO N MV 69
70
IO N MV 274
318
IO P MV 71
72
IO P MV 276
GND 73
74
GND
288
IO N MV 75
76
IO N MV 229
289
IO P MV 77
78
IO P MV 235
GND 79
80
GND
Control
Delay [ps] +3.3V 1
2
VDD Delay [ps]
+3.3V 3
4
VDD
+3.3V 5
6
VDD
+3.3V 7
8
VDD
+3.3V 9
10
VDD
+3.3V 11
12
VDD
+3.3V 13
14
VDD
+3.3V 15
16
VDD
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
444
IO N 29
30
IO N 524
454
IO P 31
32
IO P 506
397
IO N 33
34
IO N 510
407
IO P 35
36
IO P 498
RESET 37
38
VBSEL A
DONE 39
40
VBSEL B
PROGRAM 41
42
A1.8V
TDI* 43
44
AV P
TDO* 45
46
AV N
TMS* 47
48
AREF
TCK* 49
50
AGND
VBSEL Values
VBSEL A
VBSEL B
MV VCCO
floating
floating
3.3
low
low
3.3
low
high
3.3
high
low
1.8
high
high
2.5
VBSEL B
VBSEL A
2.5
low = 0-0.9 volts
Legend
IO Standard IO. SDA and SCL also connect to the QWIIC connector. The 1.35V
pins are not 3.3V tolerant
IO N/P Differential capable IO
MRCC/SRCC Clock capable input. Single ended clocks must go to the P pin of the pair
Multi-voltage Multi-voltage pin. The VCCO for these pins is controllable via VBSEL A and VBSEL
B
Analog Analog signal. IO N/P A and AV P/N are 1V inputs
CONFIG Configuration signal
+3.3V 3.3V output
VDD 5V-12V board power. When plugged into USB, this can supply 5V. The USB port is protected against
higher voltages
GND Ground
† Delays include trace and package delays
* JTAG pins will be reordered to match the Au on rev B
Bottom Pinout Table
The bottom side pin numbers are bank numbers. Depending on your connector footprint, the corresponding connector pin number may be mirrored.
Bank A
Delay [ps] GND 1
2
GND Delay [ps]
500
IO N 3
4
IO N 466
500
IO P 5
6
IO P 469
GND 7
8
GND
196
IO N 9
10
IO N 237
202
IO P 11
12
IO P 238
GND 13
14
GND
208
IO N 15
16
IO N 265
199
IO P 17
18
IO P 266
GND 19
20
GND
235
IO N 21
22
IO N 259
236
IO P 23
24
IO P 263
GND 25
26
GND
236
IO N 27
28
IO N 263
239
IO P 29
30
IO P 269
GND 31
32
GND
272
IO N 33
34
IO N 294
267
IO P 35
36
IO P 284
GND 37
38
GND
270
IO N - MRCC 39
40
IO N - SRCC 411
277
IO P - MRCC 41
42
IO P - SRCC 407
GND 43
44
GND
251
IO N - MRCC 45
46
IO N - SRCC 249
250
IO P - MRCC 47
48
IO P - SRCC 256
GND 49
50
GND
251
IO N 51
52
IO N 265
255
IO P 53
54
IO P 269
GND 55
56
GND
246
IO N 57
58
IO N 303
250
IO P 59
60
IO P 300
GND 61
62
GND
263
IO N 63
64
IO N 265
267
IO P 65
66
IO P 275
GND 67
68
GND
286
IO N 69
70
IO N 439
279
IO P 71
72
IO P 425
GND 73
74
GND
292
IO N 75
76
IO N 344
305
IO P 77
78
IO P 353
GND 79
80
GND
Bank B
Delay [ps] GND 1
2
GND Delay [ps]
279
IO N 3
4
IO N 210
287
IO P 5
6
IO P 220
GND 7
8
GND
216
IO N 9
10
IO N 230
214
IO P 11
12
IO P 232
GND 13
14
GND
262
IO N 15
16
IO N 333
268
IO P 17
18
IO P 333
GND 19
20
GND
391
IO N 21
22
IO N 220
400
IO P 23
24
IO P 219
GND 25
26
GND
370
IO N 27
28
IO N 254
370
IO P 29
30
IO P 258
GND 31
32
GND
353
IO N 33
34
IO N 281
356
IO P 35
36
IO P 282
GND 37
38
GND
381
IO N - MRCC 39
40
IO N - SRCC 319
378
IO P - MRCC 41
42
IO P - SRCC 324
GND 43
44
GND
382
IO N - MRCC 45
46
IO N - SRCC 347
382
IO P - MRCC 47
48
IO P - SRCC 350
GND 49
50
GND
485
MGT CLK0 N 51
52
MGT CLK1 N 462
479
MGT CLK0 P 53
54
MGT CLK1 P 460
GND 55
56
GND
518
MGT TX0 N 57
58
MGT RX0 N 486
518
MGT TX0 P 59
60
MGT RX0 P 485
GND 61
62
GND
487
MGT TX1 N 63
64
MGT RX1 N 476
485
MGT TX1 P 65
66
MGT RX1 P 474
GND 67
68
GND
494
MGT TX2 N 69
70
MGT RX2 N 492
492
MGT TX2 P 71
72
MGT RX2 P 489
GND 73
74
GND
467
MGT TX3 N 75
76
MGT RX3 N 470
465
MGT TX3 P 77
78
MGT RX3 P 468
GND 79
80
GND
Control
Delay [ps] +3.3V 1
2
VDD Delay [ps]
+3.3V 3
4
VDD
+3.3V 5
6
VDD
+3.3V 7
8
VDD
+3.3V 9
10
VDD
+3.3V 11
12
VDD
+3.3V 13
14
VDD
+3.3V 15
16
VDD
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
410
IO N 29
30
IO N 420
405
IO P 31
32
IO P 430
362
IO N 33
34
IO N 409
362
IO P 35
36
IO P 407
RESET 37
38
VBSEL A
DONE 39
40
VBSEL B
PROGRAM 41
42
A1.8V
TDI* 43
44
AV P
TDO* 45
46
AV N
TMS* 47
48
AREF
TCK* 49
50
AGND
VBSEL Values
VBSEL A
VBSEL B
MV VCCO
floating
floating
3.3
low
low
3.3
low
high
3.3
high
low
1.8
high
high
2.5
VBSEL B
VBSEL A
2.5
low = 0-0.9 volts
Legend
IO Standard IO. SDA and SCL also connect to the QWIIC connector. The 1.35V
pins are not 3.3V tolerant
IO N/P Differential capable IO
MRCC/SRCC Clock capable input. Single ended clocks must go to the P pin of the pair
MGT Multi-Gigabit Transceiver
Multi-voltage Multi-voltage pin. The VCCO for these pins is controllable via VBSEL A and VBSEL
B
Analog Analog signal. IO N/P A and AV P/N are 1V inputs
CONFIG Configuration signal
+3.3V 3.3V output
VDD 5V-12V board power. When plugged into USB, this can supply 5V. The USB port is protected against
higher voltages
GND Ground
† Delays include trace and package delays
* JTAG pins will be reordered to match the Au on rev B
Io
Io Schematic
Pinout Table
Bank A
GND 1
2
GND
Seg B 3
4
Anode 4
Seg F 5
6
Anode 3
GND 7
8
GND
Seg A 9
10
Anode 1
Seg E 11
12
Anode 2
GND 13
14
GND
Seg D 15
16
Left Button
Seg DP 17
18
Bottom Button
GND 19
20
GND
Seg C 21
22
Center Button
Seg G 23
24
Top Button
GND 25
26
GND
LED 22 27
28
Right Button
LED 21 29
30
LED 23
GND 31
32
GND
LED 20 33
34
LED 24
LED 19 35
36
DIP 11
GND 37
38
GND
LED 18 39
40
DIP 10
LED 17 41
42
DIP 9
GND 43
44
GND
LED 16 45
46
DIP 8
LED 15 47
48
DIP 7
GND 49
50
GND
LED 14 51
52
DIP 6
LED 13 53
54
DIP 5
GND 55
56
GND
LED 12 57
58
DIP 4
LED 11 59
60
DIP 3
GND 61
62
GND
LED 10 63
64
DIP 2
LED 9 65
66
DIP 1
GND 67
68
GND
LED 8 69
70
LED 1
LED 7 71
72
LED 2
GND 73
74
GND
LED 6 75
76
LED 3
LED 5 77
78
LED 4
GND 79
80
GND
Bank B
GND 1
2
GND
DIP 18 3
4
DIP 17
DIP 19 5
6
DIP 16
GND 7
8
GND
DIP 20 9
10
DIP 15
DIP 21 11
12
DIP 14
GND 13
14
GND
DIP 22 15
16
DIP 13
DIP 23 17
18
DIP 12
GND 19
20
GND
DIP 24 21
22
-
- 23
24
-
GND 25
26
GND
- 27
28
-
- 29
30
-
GND 31
32
GND
- 33
34
-
- 35
36
-
GND 37
38
GND
- 39
40
-
- 41
42
-
GND 43
44
GND
- 45
46
-
- 47
48
-
GND 49
50
GND
- 51
52
-
- 53
54
-
GND 55
56
GND
- 57
58
-
- 59
60
-
GND 61
62
GND
- 63
64
-
- 65
66
-
GND 67
68
GND
- 69
70
-
- 71
72
-
GND 73
74
GND
- 75
76
-
- 77
78
-
GND 79
80
GND
Control
+3.3V 1
2
-
+3.3V 3
4
-
+3.3V 5
6
-
+3.3V 7
8
-
+3.3V 9
10
-
+3.3V 11
12
-
+3.3V 13
14
-
+3.3V 15
16
-
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
- 29
30
-
- 31
32
-
- 33
34
-
- 35
36
-
- 37
38
-
- 39
40
-
- 41
42
-
- 43
44
-
- 45
46
-
- 47
48
-
- 49
50
-
Legend
Signal IO signal used by the board
+3.3V 3.3V
GND Ground
- No connection
Hd
Hd Schematic
Pinout Table
Bank A
GND 1
2
GND
- 3
4
-
- 5
6
-
GND 7
8
GND
- 9
10
-
- 11
12
-
GND 13
14
GND
- 15
16
-
- 17
18
-
GND 19
20
GND
- 21
22
-
- 23
24
-
GND 25
26
GND
- 27
28
-
- 29
30
-
GND 31
32
GND
- 33
34
-
- 35
36
-
GND 37
38
GND
- 39
40
-
- 41
42
-
GND 43
44
GND
CLK 2 N 45
46
CLK 1 N
CLK 2 P 47
48
CLK 1 P
GND 49
50
GND
D0 2 N 51
52
D0 1 N
D0 2 P 53
54
D0 1 P
GND 55
56
GND
D1 2 N 57
58
D1 1 N
D1 2 P 59
60
D1 1 P
GND 61
62
GND
D2 2 N 63
64
D2 1 N
D2 2 P 65
66
D2 1 P
GND 67
68
GND
SDA 2 69
70
SDA 1
SCL 2 71
72
SCL 1
GND 73
74
GND
CEC 2 75
76
CEC 1
HP 2 77
78
HP 1
GND 79
80
GND
Bank B
GND 1
2
GND
- 3
4
-
- 5
6
-
GND 7
8
GND
- 9
10
-
- 11
12
-
GND 13
14
GND
- 15
16
-
- 17
18
-
GND 19
20
GND
- 21
22
-
- 23
24
-
GND 25
26
GND
- 27
28
-
- 29
30
-
GND 31
32
GND
- 33
34
-
- 35
36
-
GND 37
38
GND
- 39
40
-
- 41
42
-
GND 43
44
GND
- 45
46
-
- 47
48
-
GND 49
50
GND
- 51
52
-
- 53
54
-
GND 55
56
GND
- 57
58
-
- 59
60
-
GND 61
62
GND
- 63
64
-
- 65
66
-
GND 67
68
GND
- 69
70
-
- 71
72
-
GND 73
74
GND
- 75
76
-
- 77
78
-
GND 79
80
GND
Control
+3.3V 1
2
-
+3.3V 3
4
-
+3.3V 5
6
-
+3.3V 7
8
-
+3.3V 9
10
-
+3.3V 11
12
-
+3.3V 13
14
-
+3.3V 15
16
-
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
- 29
30
-
- 31
32
-
- 33
34
-
- 35
36
-
- 37
38
-
- 39
40
-
- 41
42
-
- 43
44
-
- 45
46
-
- 47
48
-
- 49
50
-
Legend
Signal IO signal used by the board
Signal N/P Differential signal used by the board
Signal N/P Differential clock used by the board
+3.3V 3.3V
GND Ground
- No internal connection but passed through top and bottom connectors
Ft
Ft Schematic
Pinout Table
Bank A
GND 1
2
GND
!Wakeup 3
4
OE
!Reset 5
6
RD
GND 7
8
GND
WR 9
10
RXF
BE1 11
12
TXE
GND 13
14
GND
BE0 15
16
D15
D13 17
18
D14
GND 19
20
GND
D10 21
22
D12
D9 23
24
D11
GND 25
26
GND
D6 27
28
D8
D5 29
30
D7
GND 31
32
GND
D2 33
34
D4
D1 35
36
D3
GND 37
38
GND
D0 39
40
-
CLK 41
42
-
GND 43
44
GND
- 45
46
-
- 47
48
-
GND 49
50
GND
- 51
52
-
- 53
54
-
GND 55
56
GND
- 57
58
-
- 59
60
-
GND 61
62
GND
- 63
64
-
- 65
66
-
GND 67
68
GND
- 69
70
-
- 71
72
-
GND 73
74
GND
- 75
76
-
- 77
78
-
GND 79
80
GND
Bank B
GND 1
2
GND
- 3
4
-
- 5
6
-
GND 7
8
GND
- 9
10
-
- 11
12
-
GND 13
14
GND
- 15
16
-
- 17
18
-
GND 19
20
GND
- 21
22
-
- 23
24
-
GND 25
26
GND
- 27
28
-
- 29
30
-
GND 31
32
GND
- 33
34
-
- 35
36
-
GND 37
38
GND
- 39
40
-
- 41
42
-
GND 43
44
GND
- 45
46
-
- 47
48
-
GND 49
50
GND
- 51
52
-
- 53
54
-
GND 55
56
GND
- 57
58
-
- 59
60
-
GND 61
62
GND
- 63
64
-
- 65
66
-
GND 67
68
GND
- 69
70
-
- 71
72
-
GND 73
74
GND
- 75
76
-
- 77
78
-
GND 79
80
GND
Control
+3.3V 1
2
VDD
+3.3V 3
4
VDD
+3.3V 5
6
VDD
+3.3V 7
8
VDD
+3.3V 9
10
VDD
+3.3V 11
12
VDD
+3.3V 13
14
VDD
+3.3V 15
16
VDD
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
- 29
30
-
- 31
32
-
- 33
34
-
- 35
36
-
- 37
38
-
- 39
40
-
- 41
42
-
- 43
44
-
- 45
46
-
- 47
48
-
- 49
50
-
Legend
Signal IO signal used by the board
Signal Clock signal used by the board
+3.3V 3.3V
VDD 5V-12V board power. When plugged into USB, this can supply 5V. The USB port is protected against
higher voltages
GND Ground
- No internal connection but passed through top and bottom connectors
Ft+
Ft+ Schematic
Pinout Table
Bank A
GND 1
2
GND
!Wakeup 3
4
OE
!Reset 5
6
RD
GND 7
8
GND
WR 9
10
RXF
BE3 11
12
TXE
GND 13
14
GND
BE0 15
16
BE2
D31 17
18
BE1
GND 19
20
GND
D28 21
22
D30
D27 23
24
D29
GND 25
26
GND
D24 27
28
D26
D23 29
30
D25
GND 31
32
GND
D20 33
34
D22
D19 35
36
D21
GND 37
38
GND
D16 39
40
D18
CLK 41
42
D17
GND 43
44
GND
- 45
46
-
- 47
48
-
GND 49
50
GND
- 51
52
-
- 53
54
-
GND 55
56
GND
- 57
58
-
- 59
60
-
GND 61
62
GND
- 63
64
-
- 65
66
-
GND 67
68
GND
- 69
70
-
- 71
72
-
GND 73
74
GND
- 75
76
-
- 77
78
-
GND 79
80
GND
Bank B
GND 1
2
GND
D0 3
4
D2
D1 5
6
D3
GND 7
8
GND
D4 9
10
D6
D5 11
12
D7
GND 13
14
GND
D8 15
16
D10
D9 17
18
D11
GND 19
20
GND
D12 21
22
D14
D13 23
24
D15
GND 25
26
GND
- 27
28
-
- 29
30
-
GND 31
32
GND
- 33
34
-
- 35
36
-
GND 37
38
GND
- 39
40
-
- 41
42
-
GND 43
44
GND
- 45
46
-
- 47
48
-
GND 49
50
GND
- 51
52
-
- 53
54
-
GND 55
56
GND
- 57
58
-
- 59
60
-
GND 61
62
GND
- 63
64
-
- 65
66
-
GND 67
68
GND
- 69
70
-
- 71
72
-
GND 73
74
GND
- 75
76
-
- 77
78
-
GND 79
80
GND
Control
+3.3V 1
2
VDD
+3.3V 3
4
VDD
+3.3V 5
6
VDD
+3.3V 7
8
VDD
+3.3V 9
10
VDD
+3.3V 11
12
VDD
+3.3V 13
14
VDD
+3.3V 15
16
VDD
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
- 29
30
-
- 31
32
-
- 33
34
-
- 35
36
-
- 37
38
-
- 39
40
-
- 41
42
-
- 43
44
-
- 45
46
-
- 47
48
-
- 49
50
-
Legend
Signal IO signal used by the board
Signal Clock signal used by the board
+3.3V 3.3V
VDD 5V-12V board power. When plugged into USB, this can supply 5V. The USB port is protected against
higher voltages
GND Ground
- No internal connection but passed through top and bottom connectors
Other Schematics
PCB Layout
Alchitry V2 Element Libraries
VIDEO
These are libraries that already have the connectors in the right place and the pins labeled with the signal names.
3D Models
