This tutorial goes over all the information you need to create your own custom elements.
Pinout
The Alchitry V2 boards have
three DF40
connectors on a side.
The 50-pin connector is the Control header.
It has pins for power and miscellaneous control and status pins.
The two 80-pin connectors have up to 52 IO pins on each with the remaining pins being used as grounds.
The connector closest to the Control header is Bank A and the other is Bank B .
The 50-pin connector is DF40HC(4.0)-50DS-0.4V(51) when used on the top and the mating DF40C-50DP-0.4V(51) when on
the bottom.
The 80-pin connectors are DF40HC(4.0)-80DS-0.4V(51) when used on the top and the mating DF40C-80DP-0.4V(51) when on
the bottom.
Pin 1 of each connector is at the bottom left for each in the image above.
The pinout of each board follows a general template, but they all vary a little from each other.
See below for the full pinouts.
Cu
Schematic
Pinout Table
Show Trace Lengths
Bank A
Length [mm] GND 1
2
GND Length [mm]
17.29
IO 3
4
IO 28.48
18.24
IO 5
6
IO 26.76
GND 7
8
GND
16.64
IO 9
10
IO 28.06
16.07
IO 11
12
IO 26.93
GND 13
14
GND
18.67
IO 15
16
IO 26.30
16.45
IO 17
18
IO 25.27
GND 19
20
GND
17.52
IO 21
22
IO 27.23
16.48
IO 23
24
IO 25.04
GND 25
26
GND
17.81
IO 27
28
IO 26.05
16.77
IO 29
30
IO 25.53
GND 31
32
GND
18.10
IO 33
34
IO 22.22
17.06
IO 35
36
IO 22.22
GND 37
38
GND
18.39
IO 39
40
IO 22.78
17.35
IO - GBIN 41
42
IO - GBIN 32.61
GND 43
44
GND
18.68
IO 45
46
IO 21.76
17.64
IO - GBIN 47
48
IO - GBIN 32.21
GND 49
50
GND
17.35
IO 51
52
IO 22.18
18.72
IO 53
54
IO 22.64
GND 55
56
GND
17.64
IO 57
58
IO 24.03
19.01
IO 59
60
IO 24.55
GND 61
62
GND
17.93
IO 63
64
IO 25.47
25.95
IO 65
66
IO 26.06
GND 67
68
GND
25.93
IO 69
70
IO 24.38
25.50
IO 71
72
IO 23.61
GND 73
74
GND
27.23
IO 75
76
IO 25.55
26.77
IO 77
78
IO 24.88
GND 79
80
GND
Bank B
Length [mm] GND 1
2
GND Length [mm]
22.20
IO 3
4
IO 15.13
23.61
IO 5
6
IO 17.00
GND 7
8
GND
21.79
IO 9
10
IO 15.42
23.28
IO 11
12
IO 16.58
GND 13
14
GND
21.37
IO 15
16
IO 15.71
20.77
IO 17
18
IO 17.17
GND 19
20
GND
21.51
IO 21
22
IO 16.00
22.28
IO 23
24
IO 16.84
GND 25
26
GND
21.88
IO 27
28
IO 15.67
22.92
IO 29
30
IO 17.05
GND 31
32
GND
39.54
IO - SDA 33
34
IO - CBSEL0 19.84
40.38
IO - SCL 35
36
IO - CBSEL1 16.92
GND 37
38
GND
22.62
IO 39
40
-
23.77
IO - GBIN 41
42
IO - GBIN 21.63
GND 43
44
GND
- 45
46
-
- 47
48
-
GND 49
50
GND
- 51
52
-
- 53
54
-
GND 55
56
GND
- 57
58
-
- 59
60
-
GND 61
62
GND
- 63
64
-
- 65
66
-
GND 67
68
GND
- 69
70
-
- 71
72
-
GND 73
74
GND
- 75
76
-
- 77
78
-
GND 79
80
GND
Control
+3.3V 1
2
VDD
+3.3V 3
4
VDD
+3.3V 5
6
VDD
+3.3V 7
8
VDD
+3.3V 9
10
VDD
+3.3V 11
12
VDD
+3.3V 13
14
VDD
+3.3V 15
16
VDD
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
LED 0 29
30
LED 4
LED 1 31
32
LED 5
LED 2 33
34
LED 6
LED 3 35
36
LED 7
RESET 37
38
-
DONE 39
40
-
C_RESET 41
42
-
ICE SS 43
44
-
ICE SCK 45
46
-
ICE MISO 47
48
-
ICE MOSI 49
50
-
Legend
IO Standard IO. SDA and SCL also connect to the QWIIC connector
GBIN Clock capable input
CONFIG Configuration signal. CBSELn can be used to select one of multiple boot images
+3.3V 3.3V output
VDD 5V-12V board power. When plugged into USB, this can supply 5V. The USB port is protected against
higher voltages
GND Ground
- No connection
Au
Schematic
Pinout Table
Show Trace Lengths
Bank A
Length [mm] Pkg Delay [ps] GND 1
2
GND Length [mm] Pkg Delay [ps]
41.87
129.78
IO N 3
4
IO N 48.42
106.38
41.64
131.44
IO P 5
6
IO P 48.42
106.66
GND 7
8
GND
33.31
69.50
IO N 9
10
IO N 38.82
72.25
33.31
74.60
IO P 11
12
IO P 38.82
69.94
GND 13
14
GND
27.67
63.21
IO N 15
16
IO N 34.72
59.50
27.67
62.33
IO P 17
18
IO P 34.62
48.45
GND 19
20
GND
32.23
89.99
IO N 21
22
IO N 31.65
84.70
32.23
88.34
IO P 23
24
IO P 31.65
82.19
GND 25
26
GND
27.04
57.72
IO N 27
28
IO N 29.57
71.93
27.04
63.75
IO P 29
30
IO P 29.65
81.98
GND 31
32
GND
31.81
66.61
IO N 33
34
IO N 32.53
67.73
31.81
65.72
IO P 35
36
IO P 32.54
70.76
GND 37
38
GND
22.66
120.07
IO N - MRCC 39
40
IO N - SRCC 28.55
91.49
22.66
114.57
IO P - MRCC 41
42
IO P - SRCC 28.53
87.86
GND 43
44
GND
35.61
81.95
IO N - MRCC 45
46
IO N - SRCC 39.82
82.54
35.61
81.20
IO P - MRCC 47
48
IO P - SRCC 39.82
81.91
GND 49
50
GND
25.00
89.03
IO N 51
52
IO N 29.90
66.75
25.00
91.17
IO P 53
54
IO P 29.93
69.52
GND 55
56
GND
24.35
90.32
IO N A 57
58
IO N A 33.77
90.71
24.35
91.64
IO P A 59
60
IO P A 33.77
89.71
GND 61
62
GND
30.47
94.12
IO N A 63
64
IO N A 33.32
99.38
30.47
84.98
IO P A 65
66
IO P A 33.32
90.61
GND 67
68
GND
29.82
96.32
IO N A 69
70
IO N A 33.02
87.78
29.82
99.54
IO P A 71
72
IO P A 33.02
84.57
GND 73
74
GND
26.66
86.62
IO N A 75
76
IO N A 31.26
96.37
26.41
86.53
IO P A 77
78
IO P A 31.32
97.53
GND 79
80
GND
Bank B
Length [mm] Pkg Delay [ps] GND 1
2
GND Length [mm] Pkg Delay [ps]
17.51
109.30
IO N 3
4
IO N 12.11
107.25
17.51
111.65
IO P 5
6
IO P 12.11
108.71
GND 7
8
GND
22.97
108.47
IO N 9
10
IO N 10.96
110.08
22.97
104.86
IO P 11
12
IO P 10.96
111.65
GND 13
14
GND
21.37
119.33
IO N 15
16
IO N 11.04
95.83
21.37
119.49
IO P 17
18
IO P 11.04
101.88
GND 19
20
GND
22.19
116.81
IO N 21
22
IO N 11.81
97.86
22.19
122.33
IO P 23
24
IO P 11.81
95.53
GND 25
26
GND
22.95
108.93
IO N 27
28
IO N 12.99
85.37
22.95
114.03
IO P 29
30
IO P 12.99
83.20
GND 31
32
GND
43.26
41.65
IO - SDA 33
34
IO N 15.06
93.08
50.50
43.91
IO - SCL 35
36
IO P 15.06
102.45
GND 37
38
GND
24.62
124.53
IO N - SRCC 39
40
IO N - SRCC 17.67
116.36
24.59
129.84
IO P - SRCC 41
42
IO P - SRCC 17.67
111.92
GND 43
44
GND
25.16
112.96
IO N - MRCC 45
46
IO - 1.35V 28.30
96.18
25.16
114.40
IO P - MRCC 47
48
IO - 1.35V 29.39
63.97
GND 49
50
GND
36.36
73.22
IO N MV 51
52
IO N MV 29.23
74.89
36.34
79.34
IO P MV 53
54
IO P MV 29.23
77.27
GND 55
56
GND
33.89
62.94
IO N MV 57
58
IO N MV 28.79
86.39
33.89
63.95
IO P MV 59
60
IO P MV 28.79
83.34
GND 61
62
GND
34.36
69.88
IO N MV 63
64
IO N MV 28.48
87.35
34.36
65.03
IO P MV 65
66
IO P MV 28.40
85.92
GND 67
68
GND
41.44
55.09
IO N MV 69
70
IO N MV 28.31
85.02
41.29
50.97
IO P MV 71
72
IO P MV 28.31
84.47
GND 73
74
GND
40.24
35.45
IO N MV 75
76
IO N MV 33.92
46.51
37.79
57.82
IO P MV 77
78
IO P MV 33.92
47.75
GND 79
80
GND
Control
+3.3V 1
2
VDD
+3.3V 3
4
VDD
+3.3V 5
6
VDD
+3.3V 7
8
VDD
+3.3V 9
10
VDD
+3.3V 11
12
VDD
+3.3V 13
14
VDD
+3.3V 15
16
VDD
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
LED 0 29
30
LED 4
LED 1 31
32
LED 5
LED 2 33
34
LED 6
LED 3 35
36
LED 7
RESET 37
38
VBSEL A
DONE 39
40
VBSEL B
PROGRAM 41
42
A1.8V
TMS 43
44
AV P
TCK 45
46
AV N
TDI 47
48
AREF
TDO 49
50
AGND
VBSEL Values
VBSEL A
VBSEL B
MV VCCO
floating
floating
3.3
low
low
3.3
low
high
3.3
high
low
1.8
high
high
2.5
VBSEL B
VBSEL A
2.5
low = 0-0.9 volts
Legend
IO Standard IO. SDA and SCL also connect to the QWIIC connector. The 1.35V
pins are not 3.3V tolerant
IO N/P Differential capable IO
MRCC/SRCC Clock capable input. Single ended clocks must go to the P pin of the pair
Multi-voltage Multi-voltage pin. The VCCO for these pins is controllable via VBSEL A and VBSEL
B
Analog Analog signal. IO N/P A and AV P/N are 1V inputs
CONFIG Configuration signal
+3.3V 3.3V output
VDD 5V-12V board power. When plugged into USB, this can supply 5V. The USB port is protected against
higher voltages
GND Ground
Pt
Schematic
Top Pinout Table
Show Trace Lengths
Bank A
Length [mm] Pkg Delay [ps] GND 1
2
GND Length [mm] Pkg Delay [ps]
41.97
160.93
IO N 3
4
IO N 46.48
140.33
42.49
160.51
IO P 5
6
IO P 47.23
141.10
GND 7
8
GND
26.13
100.15
IO N 9
10
IO N 43.19
102.69
26.59
103.97
IO P 11
12
IO P 44.15
105.45
GND 13
14
GND
36.11
94.89
IO N 15
16
IO N 38.38
100.70
36.43
95.90
IO P 17
18
IO P 38.66
103.41
GND 19
20
GND
30.12
81.51
IO N 21
22
IO N 32.74
114.73
30.42
83.42
IO P 23
24
IO P 33.04
113.11
GND 25
26
GND
35.67
90.47
IO N 27
28
IO N 40.39
80.23
35.67
89.94
IO P 29
30
IO P 40.09
83.67
GND 31
32
GND
49.55
92.92
IO N 33
34
IO N 51.42
92.23
48.37
96.45
IO P 35
36
IO P 50.19
88.98
GND 37
38
GND
33.93
82.10
IO N - MRCC 39
40
IO N - SRCC 43.00
93.14
34.23
81.40
IO P - MRCC 41
42
IO P - SRCC 43.94
89.75
GND 43
44
GND
36.46
78.85
IO N - MRCC 45
46
IO N - SRCC 52.28
91.92
36.73
79.24
IO P - MRCC 47
48
IO P - SRCC 53.29
93.60
GND 49
50
GND
52.46
107.58
IO N 51
52
IO N 60.32
106.81
52.76
117.60
IO P 53
54
IO P 59.05
104.50
GND 55
56
GND
32.14
112.74
IO N A 57
58
IO N A 38.75
121.25
32.45
113.24
IO P A 59
60
IO P A 39.04
120.61
GND 61
62
GND
39.66
101.52
IO N A 63
64
IO N A 41.45
105.78
39.93
98.92
IO P A 65
66
IO P A 41.74
106.69
GND 67
68
GND
38.51
84.96
IO N A 69
70
IO N A 46.67
89.49
38.81
83.31
IO P A 71
72
IO P A 47.03
88.89
GND 73
74
GND
46.25
108.36
IO N A 75
76
IO N A 48.80
94.36
46.59
109.24
IO P A 77
78
IO P A 49.10
96.56
GND 79
80
GND
Bank B
Length [mm] Pkg Delay [ps] GND 1
2
GND Length [mm] Pkg Delay [ps]
20.00
84.02
IO N 3
4
IO N 17.15
106.08
21.10
89.12
IO P 5
6
IO P 15.75
109.23
GND 7
8
GND
30.30
85.27
IO N 9
10
IO N 16.95
89.11
30.78
82.20
IO P 11
12
IO P 17.20
81.47
GND 13
14
GND
15.57
131.07
IO N 15
16
IO N 15.18
80.63
15.82
129.79
IO P 17
18
IO P 15.45
80.02
GND 19
20
GND
14.67
144.25
IO N 21
22
IO N - SRCC 17.90
127.85
15.15
146.47
IO P 23
24
IO P - SRCC 18.44
135.88
GND 25
26
GND
12.85
144.49
IO N - MRCC 27
28
IO N - SRCC 16.04
136.98
13.99
140.36
IO P - MRCC 29
30
IO P - SRCC 16.32
134.33
GND 31
32
GND
22.44
171.93
IO N MV 33
34
IO N MV 15.23
139.32
23.34
164.83
IO P MV 35
36
IO P MV 15.52
143.18
GND 37
38
GND
50.13
143.61
IO N MV - MRCC 39
40
IO N MV - SRCC 19.82
144.92
49.67
143.56
IO P MV - MRCC 41
42
IO P MV - SRCC 20.41
143.25
GND 43
44
GND
32.08
116.98
IO N MV - MRCC 45
46
IO N MV - SRCC 20.97
119.05
32.67
116.96
IO P MV - MRCC 47
48
IO P MV - SRCC 21.24
115.35
GND 49
50
GND
27.31
162.45
IO N MV 51
52
IO N MV 21.85
135.13
27.04
164.84
IO P MV 53
54
IO P MV 22.46
144.42
GND 55
56
GND
21.84
160.27
IO N MV 57
58
IO N MV 27.49
133.81
22.46
162.72
IO P MV 59
60
IO P MV 28.35
133.07
GND 61
62
GND
26.16
153.23
IO N MV 63
64
IO N MV 30.86
93.70
26.88
144.89
IO P MV 65
66
IO P MV 31.42
96.83
GND 67
68
GND
22.90
168.88
IO N MV 69
70
IO N MV 20.67
136.12
23.23
161.48
IO P MV 71
72
IO P MV 20.96
136.53
GND 73
74
GND
22.21
140.06
IO N MV 75
76
IO N MV 20.93
91.27
22.66
135.50
IO P MV 77
78
IO P MV 21.50
92.82
GND 79
80
GND
Control
Length [mm] +3.3V 1
2
VDD Length [mm]
+3.3V 3
4
VDD
+3.3V 5
6
VDD
+3.3V 7
8
VDD
+3.3V 9
10
VDD
+3.3V 11
12
VDD
+3.3V 13
14
VDD
+3.3V 15
16
VDD
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
45.90
IO N 29
30
IO N 53.51
46.48
IO P 31
32
IO P 52.61
39.46
IO N 33
34
IO N 62.25
39.16
IO P 35
36
IO P 61.72
RESET 37
38
VBSEL A
DONE 39
40
VBSEL B
PROGRAM 41
42
A1.8V
TDI* 43
44
AV P
TDO* 45
46
AV N
TMS* 47
48
AREF
TCK* 49
50
AGND
VBSEL Values
VBSEL A
VBSEL B
MV VCCO
floating
floating
3.3
low
low
3.3
low
high
3.3
high
low
1.8
high
high
2.5
VBSEL B
VBSEL A
2.5
low = 0-0.9 volts
Legend
IO Standard IO. SDA and SCL also connect to the QWIIC connector. The 1.35V
pins are not 3.3V tolerant
IO N/P Differential capable IO
MRCC/SRCC Clock capable input. Single ended clocks must go to the P pin of the pair
Multi-voltage Multi-voltage pin. The VCCO for these pins is controllable via VBSEL A and VBSEL
B
Analog Analog signal. IO N/P A and AV P/N are 1V inputs
CONFIG Configuration signal
+3.3V 3.3V output
VDD 5V-12V board power. When plugged into USB, this can supply 5V. The USB port is protected against
higher voltages
GND Ground
* JTAG pins will be reordered to match the Au on rev B
Bottom Pinout Table
Show Trace Lengths
The bottom side pin numbers are bank numbers, and the corresponding connector pin number is mirrored
(pin 1 is pin 2 and pin 2 is 1)
Bank A
Length [mm] Pkg Delay [ps] GND 1
2
GND Length [mm] Pkg Delay [ps]
46.64
167.85
IO N 3
4
IO N 45.65
142.61
46.92
166.13
IO P 5
6
IO P 46.05
143.33
GND 7
8
GND
21.29
64.15
IO N 9
10
IO N 18.80
120.99
21.47
67.91
IO P 11
12
IO P 19.38
118.68
GND 13
14
GND
15.74
113.14
IO N 15
16
IO N 22.73
122.36
15.00
109.76
IO P 17
18
IO P 23.13
121.25
GND 19
20
GND
20.51
109.01
IO N 21
22
IO N 24.89
101.37
20.72
107.99
IO P 23
24
IO P 25.79
99.80
GND 25
26
GND
18.97
118.75
IO N 27
28
IO N 24.48
108.53
19.08
121.05
IO P 29
30
IO P 24.86
113.39
GND 31
32
GND
23.21
116.38
IO N 33
34
IO N 23.19
136.20
23.70
106.47
IO P 35
36
IO P 22.60
131.00
GND 37
38
GND
24.59
114.10
IO N - MRCC 39
40
IO N - SRCC 46.27
106.42
25.62
114.04
IO P - MRCC 41
42
IO P - SRCC 45.76
106.48
GND 43
44
GND
24.31
98.63
IO N - MRCC 45
46
IO N - SRCC 25.75
88.62
24.78
94.08
IO P - MRCC 47
48
IO P - SRCC 26.05
93.65
GND 49
50
GND
26.46
69.28
IO N 51
52
IO N 23.14
108.76
27.06
68.87
IO P 53
54
IO P 23.82
108.89
GND 55
56
GND
25.46
73.46
IO N 57
58
IO N 30.75
92.02
26.22
70.39
IO P 59
60
IO P 30.22
92.97
GND 61
62
GND
25.01
91.25
IO N 63
64
IO N 22.99
109.74
25.31
93.06
IO P 65
66
IO P 23.38
117.25
GND 67
68
GND
27.76
96.01
IO N 69
70
IO N 52.13
66.16
27.09
93.10
IO P 71
72
IO P 50.36
65.38
GND 73
74
GND
30.91
80.00
IO N 75
76
IO N 35.83
93.59
31.51
88.00
IO P 77
78
IO P 36.50
97.51
GND 79
80
GND
Bank B
Length [mm] Pkg Delay [ps] GND 1
2
GND Length [mm] Pkg Delay [ps]
21.60
133.82
IO N 3
4
IO N 15.06
114.00
22.09
138.40
IO P 5
6
IO P 15.14
124.64
GND 7
8
GND
17.93
99.44
IO N 9
10
IO N 16.74
120.09
17.83
97.65
IO P 11
12
IO P 17.01
120.26
GND 13
14
GND
22.36
109.83
IO N 15
16
IO N 25.63
158.15
23.25
109.32
IO P 17
18
IO P 25.99
156.32
GND 19
20
GND
32.57
165.26
IO N 21
22
IO N 18.30
98.19
33.64
165.96
IO P 23
24
IO P 18.61
95.03
GND 25
26
GND
39.93
88.08
IO N 27
28
IO N 23.23
97.28
39.63
90.04
IO P 29
30
IO P 23.61
99.62
GND 31
32
GND
35.64
104.27
IO N 33
34
IO N 26.26
100.66
35.78
105.84
IO P 35
36
IO P 26.42
101.32
GND 37
38
GND
37.65
135.36
IO N - MRCC 39
40
IO N - SRCC 28.61
136.07
38.16
129.72
IO P - MRCC 41
42
IO P - SRCC 29.08
139.01
GND 43
44
GND
44.06
93.69
IO N - MRCC 45
46
IO N - SRCC 38.69
93.62
44.18
92.57
IO P - MRCC 47
48
IO P - SRCC 38.98
94.62
GND 49
50
GND
63.82
59.24
MGT CLK0 N 51
52
MGT CLK1 N 63.40
39.88
63.54
55.87
MGT CLK0 P 53
54
MGT CLK0 N 63.18
40.26
GND 55
56
GND
63.63
94.96
MGT TX0 N 57
58
MGT RX0 N 62.80
67.84
63.62
94.50
MGT TX0 P 59
60
MGT RX0 P 62.82
66.52
GND 61
62
GND
62.75
68.37
MGT TX1 N 63
64
MGT RX1 N 62.90
56.93
62.57
67.96
MGT TX1 P 65
66
MGT RX1 P 62.90
56.16
GND 67
68
GND
62.95
75.73
MGT TX2 N 69
70
MGT RX2 N 63.58
68.05
62.79
74.13
MGT TX2 P 71
72
MGT RX2 P 63.43
66.55
GND 73
74
GND
62.37
52.29
MGT TX3 N 75
76
MGT RX3 N 63.11
50.00
62.33
50.68
MGT TX3 P 77
78
MGT RX3 P 62.95
49.15
GND 79
80
GND
Control
Length [mm] Pkg Delay [ps] +3.3V 1
2
VDD Length [mm] Pkg Delay [ps]
+3.3V 3
4
VDD
+3.3V 5
6
VDD
+3.3V 7
8
VDD
+3.3V 9
10
VDD
+3.3V 11
12
VDD
+3.3V 13
14
VDD
+3.3V 15
16
VDD
GND 17
18
GND
GND 19
20
GND
GND 21
22
GND
GND 23
24
GND
GND 25
26
GND
GND 27
28
GND
40.91
122.54
IO N 29
30
IO N 42.52
119.15
39.94
123.56
IO P 31
32
IO P 44.36
115.80
34.39
121.91
IO N 33
34
IO N 41.32
117.65
34.55
122.65
IO P 35
36
IO P 40.50
122.63
RESET 37
38
VBSEL A
DONE 39
40
VBSEL B
PROGRAM 41
42
A1.8V
TDI* 43
44
AV P
TDO* 45
46
AV N
TMS* 47
48
AREF
TCK* 49
50
AGND
VBSEL Values
VBSEL A
VBSEL B
MV VCCO
floating
floating
3.3
low
low
3.3
low
high
3.3
high
low
1.8
high
high
2.5
VBSEL B
VBSEL A
2.5
low = 0-0.9 volts
Legend
IO Standard IO. SDA and SCL also connect to the QWIIC connector. The 1.35V
pins are not 3.3V tolerant
IO N/P Differential capable IO
MRCC/SRCC Clock capable input. Single ended clocks must go to the P pin of the pair
MGT Multi-Gigabit Transceiver
Multi-voltage Multi-voltage pin. The VCCO for these pins is controllable via VBSEL A and VBSEL
B
Analog Analog signal. IO N/P A and AV P/N are 1V inputs
CONFIG Configuration signal
+3.3V 3.3V output
VDD 5V-12V board power. When plugged into USB, this can supply 5V. The USB port is protected against
higher voltages
GND Ground
* JTAG pins will be reordered to match the Au on rev B
PCB Layout
Alchitry V2 Element Libraries
These are libraries that already have the connectors in the right place and the pins labeled with the signal names.
