Creating a Vivado Project for the Au
This tutorial is to get you familiar with how to create a project in Vivado for the Alchitry Au and the very basics of Verilog.
Tutorials
Embedded Processors
This tutorial will outline how to add a MicroBlaze MCS to your project. The MicroBlazeMCS is a 32bit microprocessor core provided by Xilinx. It will allow you to write C/C++ code that will interact with the rest of your design. While this can be very helpful in many projects, setting it up can be a bit confusing. This tutorial will hopefully demystify the process.
SDRAM
This tutorial will cover how DRAM (Dynamic Random Access Memory), or more specifically SDRAM (Synchronized DRAM), works and how you can use it in your FPGA projects.
Memory Mapping
This tutorial covers a common technique for interfacing a peripheral to a processor known as memory mapping. Memory mapping is were you break out a set of functions or settings and map them to a set of values that are selected by a given address. Typically the master is able to read and write these values however it chooses much like a block of RAM. However, these values aren't just blocks of memory, they effect some external device. Because this is used for interfacing it is sometimes called memory mapped IO.
Finite State Machines
Finite State Machines, or FSMs, are an incredibly powerful tool when designing digital circuits. This tutorial will teach what an FSM is through example. We will use a basic FSM to control a very simple robot.
FPGA Timing
Timing is a term used in digital circuits to refer to the time it takes a signal to propagate from one flip-flop, through some combinational logic, to the next flip-flop.
Using Core Generator
Core Generator (also called CoreGen) is a powerful tool provided by Xilinx to help easily and efficiently accomplish some common functions. It allows you to generate modules for things like RAMs, ROMs, clock synthesis, complicated math functions, and even basic processor cores.
